Eight words of RAM, from NAND gates and tri-state buffers

2026-08-09

Eight addressable bits. The board arrives reading itself out: a counter walks the address 0 through 7, the S2/S1/S0 lamps show which word is in play, and DOUT reports what that word holds — so the first thing you see is the memory’s own power-up contents scrolling past, one bit per clock.

Raise PICK to take the address off the counter and onto the A2/A1/A0 switches. Then put a value on DIN, raise WE, and the next clock pulse stores it; drop WE and DOUT shows whatever that word now holds. The memory itself is 85 NAND gates; the counter and the three multiplexers that hand the address back and forth bring the whole board to 145.

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How addressing actually works

Memory is not a lookup table in hardware; it is a fan-out problem. Three things have to happen at once.

Selection. A2 picks which of two four-word banks is in play. Inside each bank, a DECODE-2 turns the two low address bits into four one-hot lines, so exactly one cell is selected and the other three are not.

Writing. The write pulse is gated twice: once with WE, so nothing is stored unless you ask, and once with the clock, so storing is confined to half of each cycle rather than happening continuously. The result drives the enable of one D-LATCH — and only one, because the decoder guarantees it.

Note what that gate is not. A D-LATCH is level-sensitive: it stays transparent for the entire clock-high phase, so the cell tracks DIN the whole time the clock is up and freezes whatever DIN happened to be when the clock falls. Change DIN twice during one high phase and the second value is what sticks. Level-sensitive cells like this are what most static memory uses, though a real SRAM bit is six transistors rather than four NANDs behind a buffer. An edge-triggered cell — the D-FLOP this library also ships, two latches in series — samples at the instant of the edge and ignores the rest of the phase. That difference is the single most common source of confusion in sequential logic, and you can watch it here: it is why the accumulator in the fetch datapath is a flop and these memory cells are not.

Reading. This is the interesting half. Four cells share one output wire. They cannot all drive it, so each sits behind a TRI buffer enabled by the same one-hot line that selects it. The selected cell drives the wire; the other three disconnect entirely — not low, but floating.

That is why this simulator has a third pin state. Wire a floating output into a board output and it draws as a dashed grey line: nothing is driving it. A bus is exactly this arrangement, and it is how a processor talks to memory over shared wires without every device shouting at once.

You will not catch DOUT floating on this board, though — RAM-8X1 joins its two banks through a MUX-2, and the decoder inside each bank is strictly one-hot, so something is always driving the pin. Open a RAM-4X1 bank to see the shared wire itself, where three of the four TRI buffers are disconnected at any moment.

Things worth trying

• Leave it alone first. The scan is the demonstration: eight addresses, one per clock, each one lighting DOUT with what that cell happens to hold. Nothing was ever written — a real static memory powers up holding whatever it powers up holding, and that is what you are watching.
• Fill the whole memory in one gesture. Leave the counter scanning, raise DIN, then raise WE. Every word the scan passes is overwritten with a 1, so within one lap DOUT goes solid. Drop WE and walk it again to confirm. Then drop DIN and repeat to wipe it back to zeros. Writing to whatever address happens to be under the write pulse is a real thing real hardware does to you, not a quirk of the model.
• Take manual control. Raise PICK and the counter is ignored: the address is now the three switches, and S2/S1/S0 confirm which word you have selected. Write one bit into one address, drop PICK, and watch the scan find it — a single 1 going past in a field of zeros.
• Watch the latch be a latch. Raise PICK first so the address holds still. Pause, set an address and raise WE, then step with s until the badge reads clk 1 — the clock is high. Flip DIN and press s once: DOUT moves with it. Keep stepping until the badge reads clk 0, flip DIN again and step: nothing happens. The cell is wide open for the whole high phase and shut for the whole low one. (Stepping matters — while the sim is paused no simulation frames run, so nothing propagates until you advance it.)
• Open RAM-8X1, then a RAM-4X1 bank — that is the level the four TRI buffers live on, three of them disconnected at any moment. Carry on into DECODE-2 and then into one of its NOTs: four opens down, there is nothing left but NAND.

Built out of NAND gates and nothing else. The sandbox, the JSON module format and the rest of the library are described in Digital logic — from NAND to a computer.

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