Program counter, memory and accumulator — the fetch cycle

This is the smallest arrangement that deserves the word machine: something that keeps track of where it is, reads what it finds there, and remembers the answer. 100 NAND gates.

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Writing a program in by hand

Raise PROG. That swaps the memory’s address lines over from the counter to your switches and enables writing. Now:

  1. Set PA1/PA0 to an address (00, 01, 10, 11).
  2. Set PDIN to the bit you want stored there.
  3. Let one clock pulse pass — the bit is written.

Repeat for the other three addresses, then drop PROG. The counter takes the address lines back and starts stepping. Set the address and the bit while the clock is low: the memory cells are level-sensitive latches, so anything you change during the high phase goes straight into the selected word.

Watching it run

PC0/PC1 show where the counter is. DATA shows what memory returns at that address — it always equals the bit you stored there. ACC holds the previous fetch, one clock behind, because the accumulator is an edge-triggered D-FLOP clocked by the same signal that advances the counter: it samples what DATA was at the instant of the edge, which is the value from the previous address.

That one-cycle lag is not a bug to be papered over. It is the reason real processors have pipelines, and the reason a fetched value cannot be used in the same cycle it arrives.

What this is not

There is no instruction set here, and nothing decodes what memory returns. The fetched bit goes straight into a register; nothing interprets it as an operation. Calling this a CPU would be overselling it.

What it is, exactly, is the loop a processor is built around — address, fetch, latch — with everything visible. The honest next step is a decoder that turns fetched bits into control lines: one bit choosing whether the ALU adds or ANDs, another choosing whether the accumulator loads. That is the step from datapath to processor.

Built out of NAND gates and nothing else. The sandbox, the JSON module format and the rest of the library are described in Digital logic — from NAND to a computer.

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