PicoRV32 — live core visualizer
A self-contained, single-file visualizer of the PicoRV32
RISC-V core. The simulator is a faithful multi-cycle FSM model written in JavaScript,
walking fetch → ld_rs1 → exec → ldmem | stmem per cycle and drawing the CPU state
to a canvas — registers light up on read/write, the ALU shows operands and output,
the memory bus shows valid/ready handshakes.
Three views: Dashboard (behavioral state), Datapath (data flow on the bus),
Components (CMOS transistor view). Keyboard control: space run/pause, s step,
shift+s step ×10, r reset, v cycle views, e open the program editor.
The program editor accepts RV32I assembly with labels, comments, and common
pseudo-ops (li, j, mv, nop, bnez, beqz, ret, .word 0x…) over 256 words
(1 KB) of memory.
How it works
The standalone is a single HTML file with embedded CSS and JavaScript — no build, no server, no toolchain. It runs the same JSON-per-cycle protocol that the server-backed Verilator variant uses, but the simulator itself lives in the browser: a JS port of the testbench-program execution model.
The full project (including the Verilator-backed server-side variant, the real
picorv32.v RTL, and the Verilog testbenches) is at
YosysHQ/picorv32. The visualizer lives
under viz/standalone/index.html in that tree.