A four-bit shift register, one bit per clock

2026-08-09

Four D-FLOPs in a row, every one clocked together, each feeding the next. Whatever is on SIN when a clock edge arrives lands in the first flip-flop, and everything already inside shuffles one place along. 36 NAND gates.

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Drag the clock knob left to slow the rate down, then tap the SIN switch on and off and watch the pattern march down the four lamps. They are stacked in a column with Q0 — the first flip-flop, the one SIN feeds — at the top and Q3 at the bottom, so a bit enters at the top lamp and works its way down.

Why this matters more than it looks

A shift register is how a wire that carries one bit at a time becomes a number you can act on. Every serial protocol ends in one: bits arrive one per clock, and after eight ticks a byte is sitting there in parallel, ready to read.

Run it the other way and it is the transmitter. Load four bits, then shift them out one per clock onto a single wire.

It is also a delay line. Q3 is simply SIN from four clock ticks ago, which makes the whole thing a small memory of the recent past — the basis of edge detection, debouncing and digital filters.

Things worth trying

• Tap SIN once and watch the single bit travel down the column, Q0 → Q1 → Q2 → Q3, then off the end. Read as a number, Q3Q2Q1Q0, that is 0001, 0010, 0100, 1000, 0000 — the lamp moves down while the value doubles, which is the whole reason a shift left is a multiply by two.
• Hold SIN high for three ticks then release: the register fills from the Q0 end and empties from the Q0 end, in order.
• Compare with RING-4 in the library — the same chain with the last output wired back to the first, so the pattern circulates forever instead of falling off the end.

Built out of NAND gates and nothing else. The sandbox, the JSON module format and the rest of the library are described in Digital logic — from NAND to a computer.

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